WEBVTT

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So with presentation on, I would try to pronounce it,

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Sukkala, LA.

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Yes, please welcome, Jan, with his talk.

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Test test.

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All right.

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Thank you for coming.

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So I'm going to present Sukkala,

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which is an open source.

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She was a 3-logic analyzer.

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So I'm going to present myself.

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Present the project.

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Why is the project?

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What are the specifications?

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What I did so far and what next?

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So I'm Yans Juno.

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I'm a French guy from Granible.

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And I'm a kernel and hypervisor engineer Advaits,

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which is a French company making a hypervisor.

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Completely open source based on Zen,

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called the XCPNG.

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Thanks.

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I'm cheating a bit.

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And the timing.

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OK.

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But this talk is not related to the base company.

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It's just my own products.

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So Sukkala, I've just said, it's a logic analyzer.

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But what is a logic analyzer?

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So this slide is just to explain that.

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So this is the usual setup.

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So a logic analyzer is the thingy on the left.

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So it's a device that you connect on one end to your PC.

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And on the other end, you've got probes, prob wires,

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usually with colors that you plug on another device.

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And the goal is to analyze what's going on in the other device.

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So usually, you spin a software on your PC.

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And you will be able to display what's going on on the wires

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that you're probing, kind of like an oscilloscope,

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but for digital signals.

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So this is a tool for usually low-level embedded

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developers to kind of debug one day

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bringing up new hardware or debugging new hardware.

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Or software drivers, for instance.

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So as I said, it's a USB 3 device.

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It's a FPGA-based.

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That's a kind of chip.

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And it is open-source.

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But we are going back on this topic in the presentation.

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So how is it pronounced?

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Sukkala.

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So it's just a bad play on words.

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It is related to the company that is making a commercial

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a logic analyzer called Sally Aight.

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Yeah, so it's just a French play on words.

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Don't worry about this.

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So what's the goal of the project?

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It is to make a reasonably fast, reasonably cheap,

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an open-source logic analyzer.

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So most open-source logic analyzers today

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are usually kind of cheap, which is good.

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But they are also usually slow in the use case that I like to use,

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which is a real-time streaming.

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You've got usually two ways of using logic analyzers.

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Either the analyzer is going to sample the signals

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and buffer them on the device in some kind of memory.

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So it comes from a really fast and buffer in the memory,

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but quickly the memory is full.

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And then it has to stop sampling and send the data to the PC.

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So in this configuration the problem is that you really

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can sample for a small period.

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So you can't capture for a long time.

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So if you want to debug something that takes time to happen,

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you can't do it or you can't do it easily.

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So the streaming mode,

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it's like the device is sampling the data and

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sending them over to the PC at the same time.

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And it's able to do it for long period of times.

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Basically it could just do it forever.

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It would just feel your computer ran.

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So that's the, in my opinion, that's the use case that's the best

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to debug stuff.

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And when you're using USB 2.0,

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you can't have high sample rates for real-time streaming.

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So that's the problem I'm wanting to solve using USB 3.

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So now let's focus on USB 3 solutions.

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So I'm making a completely unfair comparison metrics table.

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So the Sali AI, which is a big commercial logic analyzer,

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it looked bad because there is already two-be-fair.

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It is a really good device.

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So it is pretty expensive.

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It's really like $1500 solution.

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It is close source, but it's really a good device.

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There is the site it solution,

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which just came out recently.

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It is extremely cheap, $69.

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But it is still kind of close source as well.

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There is also the Dream Source Lab solution,

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which is a bit in the middle, in terms of pricing.

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But it's still close source.

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And it's still great, which is what I'm trying to achieve.

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So this is completely unfair comparison.

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Everything is green, obviously, for my solution.

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And the really the goal is to have kind of the same performances.

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But be as open as possible.

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And for the price, I don't know, we'll see.

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And to not be too expensive, obviously.

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So yeah, there are also already interesting projects

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about USB 3 logic analyzer.

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There is the FX3LAFW project,

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which is an open source firmware for Cypress FX3 chips.

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That you can use on your computer using your C-Glock or PulseView.

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It does exist, but there is no open source board.

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Open source hardware for it yet.

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It's only supports the Cypress development kits,

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which is kind of cheap, so it's good,

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but it's not per se open source.

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So you can check it out if you want.

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So just to summarize, why is this project?

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You've got fast devices already, but they are close source.

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And the open source one usually are cheap and slow.

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So let's try to change that.

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So let's be more precise.

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Open source, what does it mean here on this project?

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It is a hardware project, so you have a printed secret board.

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So the idea is that the hardware should be open source.

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What does it mean?

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It means that the design files are open.

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They are on the Git repository, as well as the production files.

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So that anybody could just take the file, open them,

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modify them, learn from them,

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and also just take them, not modify them,

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and send them to production and get the device.

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The PC software to control the device is open source.

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And I'm just using the Cigroc project and the PulseU project,

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which already exists and support many logic analyzers.

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And yeah, it is open source.

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There is the firmware, because there is firmware running on the device.

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So there are many two chips on my project.

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There is a micro controller, which is running a firmware.

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So the firmware is a custom one.

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And it is also on the Git repository.

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And there is a second chip, which is an FPGA.

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It behaves differently than a micro controller,

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as it doesn't run per firmware, but it is configured

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to behave like some kind of chip.

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And so the HDL sources, the description of the hardware and the FPGA

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is also open source.

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It is based on the region.

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It is written in the main general language.

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And I'm using the LitX environment, which is a well-known open source

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and environment to make a system on FPGA.

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And also the tools.

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Tools are pretty important, because you could have open source code for your FPGA.

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But if you need to program your FPGA,

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if you need a close source tools, that's not good.

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So I've chosen the FPGA so that you could use the open source tool

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from cover to cover.

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So I'm using only Kiker, GCC, and XP, and I use this.

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And you don't have to use any proprietary tool.

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So I'm using open source hardware license.

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The weak copy left one for the printed second ball,

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for all the remaining part, LGPR.

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So it should be fast, as I said, USB3.

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So you could have like 400 mega samples per second

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and some probes to be comparable with the other solutions.

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And as I said, one of the big feature I like is real time streaming on the LGPR.

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So I'm focusing on real time streaming.

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There is no buffer on the device.

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And I'm just doing real time streaming.

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And one of the ideas I have in mind is to be extensible.

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So because I'm pretty sure that I'm trying to do something,

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I will reach some point with some features.

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But the idea is that someone should be able to improve upon it.

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To take the project, say, oh, he did it like this.

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But we can do better, we can modify, et cetera.

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So the idea, I'm using the FPGA because it truly modular.

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You can modify it, easily add elements in the pipeline

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to do, I don't know, some computing, run live encoding or filtering whatever you want.

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I'm using a language that is easy to read and to learn and easy to modify

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because it's a Python-based language to describe the FPGA.

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So it's easy to read.

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And I'm reusing already known components.

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So I'm not re-inventing the wheel so that, so yeah, it's a known ecosystem.

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Thank you.

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So I'm using lightx.

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And the architecture is as simple as possible.

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So what has been done so far?

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So the first prototype is this kind of mess.

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So it's basically just two already existing boards.

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On the left, you've got an FPGA development board, which is a nice one.

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It's the orange crab.

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And on the right, it's a hydro USB-3 board.

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It's a board featuring the mic for controller I'm using.

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And it is here just to provide USB-3 connection.

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So I'm just wiring together those two boards, and that is the first prototype.

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Second prototype, the idea was just to replace the orange crab, the FPGA part,

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and to reuse the blue board, the USB-3 board.

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So I'm not tackling all the problems at the same time.

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So I designed the board, the FPGA board, the green one,

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so that you can plug it underneath the USB-3 board.

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So that's the second prototype that allow to just get rid of the messy wiring.

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And I've just received the printed SQL board for the third prototype,

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and the bring-up has barely started.

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And so the idea of the third prototype is to have everything on one single board.

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So you've got the microcontroller on the middle and the FPGA right next to it,

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and there is just one board.

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So this is just 3D rendering.

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Let me just explain basically how things work.

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So you've got the connectors on the right.

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That's where you plug the sampling wire, the probes.

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So the data is coming from the right.

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It's entering the board.

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It's going through the divider and ESD protection.

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Then it's entering the FPGA, which is sampling the data.

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It goes down a pipeline, which I will describe inside the FPGA.

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Then the FPGA is sending the data to the microcontroller using HSPI.

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And the role of the microcontroller is just to send data over USB 3 to the computer.

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That's basically it.

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You've got the bottom of the board.

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And that's a picture of the actual board assemble.

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So that's the real thingy.

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It was nice to work and assembly it with a dog who is in the room.

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And so also there is the software part on your computer.

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When you plug the logic analyzer, you need to be able to use it.

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So I'm using Perseview and Cigrox.

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So the support is already developed.

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And it's already working.

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So this is a screenshot of Perseview capturing a serial data using the device.

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At a 128 mega sample spec and it's showing debug text.

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That's the computer host part.

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So let's focus a bit on the FPGA pipeline.

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It's quite simple.

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So this data is coming from the left.

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You've got the probe inputs.

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There is an over simpler to just use a simple data.

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Normally via DDR or twice or four per clock cycle.

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There is a hardware trigger mechanism.

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There is a sub simpler because maybe you want to drop samples.

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You don't want to, you have no use of something at 100 megahertz.

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Maybe you just need to dump sample.

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And then there is packet buffer and the HSPI transmitter to transmit to the microcontroller.

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And now let's talk about the microcontroller firmware.

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Its call is really simple.

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It's just to get data from the FPGA.

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Send it over to the PC via USB 3.

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And it also acts as a bridge between the host PC and the FPGA to send a register reads and write from the host PC to be able to start a capture, stop a capture, configure a capture etc.

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And also it is there to program the FPGA from the USB stream from the PC.

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And to have serial debugger logs.

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This is a scheme, a diagram of the whole situation for the FPGA on the right, the microcontroller on the left.

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So you see the probes on the right.

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It goes down the pipeline in the FPGA and it goes to HSPI on the MCU and USB 3 to the PC.

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And the URL link to configure the FPGA SOC.

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And so you see the diagram of the SOC.

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So what's next, bring up of the new board.

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Improved driver, the documentation, bring up new features.

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Make HSPI go faster, program the FPGA of a USB, maybe Render Syncoding,

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Lipscopal, lots of stuff to do.

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Thank you.

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Here are the link to the Git repository.