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EVEX_INSTRUCTIONS()::
# EMITTING TCVTROWD2PS (TCVTROWD2PS-512-1)
{
ICLASS:      TCVTROWD2PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x4A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=TMM_B3():r:tv:u32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32
}


# EMITTING TCVTROWD2PS (TCVTROWD2PS-512-2)
{
ICLASS:      TCVTROWD2PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf32 REG1=TMM_B3():r:tv:u32 IMM0:r:b
IFORM:       TCVTROWD2PS_ZMMf32_TMMu32_IMM8
}


# EMITTING TCVTROWPS2BF16H (TCVTROWPS2BF16H-512-1)
{
ICLASS:      TCVTROWPS2BF16H
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2BF16H_ZMMbf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2BF16H (TCVTROWPS2BF16H-512-2)
{
ICLASS:      TCVTROWPS2BF16H
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2BF16H_ZMMbf16_TMMf32_IMM8
}


# EMITTING TCVTROWPS2BF16L (TCVTROWPS2BF16L-512-1)
{
ICLASS:      TCVTROWPS2BF16L
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2BF16L_ZMMbf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2BF16L (TCVTROWPS2BF16L-512-2)
{
ICLASS:      TCVTROWPS2BF16L
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x77 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2BF16L_ZMMbf16_TMMf32_IMM8
}


# EMITTING TCVTROWPS2PHH (TCVTROWPS2PHH-512-1)
{
ICLASS:      TCVTROWPS2PHH
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D VNP V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2PHH (TCVTROWPS2PHH-512-2)
{
ICLASS:      TCVTROWPS2PHH
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8
}


# EMITTING TCVTROWPS2PHL (TCVTROWPS2PHL-512-1)
{
ICLASS:      TCVTROWPS2PHL
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x6D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
IFORM:       TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32
}


# EMITTING TCVTROWPS2PHL (TCVTROWPS2PHL-512-2)
{
ICLASS:      TCVTROWPS2PHL
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x77 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
IFORM:       TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8
}


# EMITTING TILEMOVROW (TILEMOVROW-512-1)
{
ICLASS:      TILEMOVROW
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E7-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x07 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=TMM_B3():r:tv:u8 IMM0:r:b
IFORM:       TILEMOVROW_ZMMu8_TMMu8_IMM8
}


# EMITTING TILEMOVROW (TILEMOVROW-512-2)
{
ICLASS:      TILEMOVROW
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_AVX512
EXCEPTIONS:  AMX-E8-EVEX
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX 
PATTERN:     EVV 0x4A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=TMM_B3():r:tv:u8 REG2=GPR32_N():r:d:u32
IFORM:       TILEMOVROW_ZMMu8_TMMu8_GPR32u32
}


AVX_INSTRUCTIONS()::
# EMITTING TDPBF8PS (TDPBF8PS-128-1)
{
ICLASS:      TDPBF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD VNP MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4bf8 REG2=TMM_N():r:tv:4bf8
IFORM:       TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8
}


# EMITTING TDPBHF8PS (TDPBHF8PS-128-1)
{
ICLASS:      TDPBHF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD VF2 MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4bf8 REG2=TMM_N():r:tv:4hf8
IFORM:       TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8
}


# EMITTING TDPHBF8PS (TDPHBF8PS-128-1)
{
ICLASS:      TDPHBF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD VF3 MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4hf8 REG2=TMM_N():r:tv:4bf8
IFORM:       TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8
}


# EMITTING TDPHF8PS (TDPHF8PS-128-1)
{
ICLASS:      TDPHF8PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_FP8
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  FIXED_ROUNDING_RNE NOTSX NO_REG_MATCH 
PATTERN:     VV1 0xFD V66 MAP5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:4hf8 REG2=TMM_N():r:tv:4hf8
IFORM:       TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8
}


# EMITTING TILELOADDRS (TILELOADDRS-128-1)
{
ICLASS:      TILELOADDRS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_MOVRS
EXCEPTIONS:  AMX-E3
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x4A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADDRS_TMMu32_MEMu32
}


# EMITTING TILELOADDRST1 (TILELOADDRST1-128-1)
{
ICLASS:      TILELOADDRST1
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_MOVRS
EXCEPTIONS:  AMX-E3
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
PATTERN:     VV1 0x4A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
IFORM:       TILELOADDRST1_TMMu32_MEMu32
}


# EMITTING TMMULTF32PS (TMMULTF32PS-128-1)
{
ICLASS:      TMMULTF32PS
CPL:         3
CATEGORY:    AMX_TILE
EXTENSION:   AMX_TILE
ISA_SET:     AMX_TF32
EXCEPTIONS:  AMX-E4
REAL_OPCODE: Y
ATTRIBUTES:  NOTSX NO_REG_MATCH 
PATTERN:     VV1 0x48 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:f32 REG2=TMM_N():r:tv:f32
IFORM:       TMMULTF32PS_TMMf32_TMMf32_TMMf32
}


