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EVEX_INSTRUCTIONS()::
# EMITTING VADDSD (VADDSD-128-1-0)
{
ICLASS:      VADDSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VADDSH (VADDSH-128-1-0)
{
ICLASS:      VADDSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VADDSS (VADDSS-128-1-0)
{
ICLASS:      VADDSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCMPSD (VCMPSD-128-1-0)
{
ICLASS:      VCMPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC
}


# EMITTING VCMPSH (VCMPSH-128-1-0)
{
ICLASS:      VCMPSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC
}


# EMITTING VCMPSS (VCMPSS-128-1-0)
{
ICLASS:      VCMPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() ZEROING=0 UIMM8()
OPERANDS:    REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC
}


# EMITTING VCOMISD (VCOMISD-128-1-0)
{
ICLASS:      VCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCOMISH (VCOMISH-128-1-0)
{
ICLASS:      VCOMISH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCOMISS (VCOMISS-128-1-0)
{
ICLASS:      VCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2SH (VCVTSD2SH-128-1-0)
{
ICLASS:      VCVTSD2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2SI (VCVTSD2SI-128-1-mode64-0)
{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2SI (VCVTSD2SI-128-1-not64-0)
{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2SI (VCVTSD2SI-128-2-0)
{
ICLASS:      VCVTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2SS (VCVTSD2SS-128-1-0)
{
ICLASS:      VCVTSD2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2USI (VCVTSD2USI-128-1-mode64-0)
{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2USI (VCVTSD2USI-128-1-not64-0)
{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSD2USI (VCVTSD2USI-128-2-0)
{
ICLASS:      VCVTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM:       VCVTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2SD (VCVTSH2SD-128-1-0)
{
ICLASS:      VCVTSH2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:     EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-mode64-0)
{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-not64-0)
{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2SI (VCVTSH2SI-128-2-0)
{
ICLASS:      VCVTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2SS (VCVTSH2SS-128-1-0)
{
ICLASS:      VCVTSH2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ 
PATTERN:     EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16
IFORM:       VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-mode64-0)
{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-not64-0)
{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSH2USI (VCVTSH2USI-128-2-0)
{
ICLASS:      VCVTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
IFORM:       VCVTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SD (VCVTSI2SD-128-1-mode64-0)
{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR 
PATTERN:     EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SD (VCVTSI2SD-128-1-not64-0)
{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR 
PATTERN:     EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SD (VCVTSI2SD-128-2-0)
{
ICLASS:      VCVTSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-mode64-0)
{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-not64-0)
{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SH (VCVTSI2SH-128-2-0)
{
ICLASS:      VCVTSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SS (VCVTSI2SS-128-1-mode64-0)
{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SS (VCVTSI2SS-128-1-not64-0)
{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_SCALAR_RC
}


# EMITTING VCVTSI2SS (VCVTSI2SS-128-2-0)
{
ICLASS:      VCVTSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
IFORM:       VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2SD (VCVTSS2SD-128-1-0)
{
ICLASS:      VCVTSS2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2SH (VCVTSS2SH-128-1-0)
{
ICLASS:      VCVTSS2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2SI (VCVTSS2SI-128-1-mode64-0)
{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2SI (VCVTSS2SI-128-1-not64-0)
{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2SI (VCVTSS2SI-128-2-0)
{
ICLASS:      VCVTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2USI (VCVTSS2USI-128-1-mode64-0)
{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2USI (VCVTSS2USI-128-1-not64-0)
{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTSS2USI (VCVTSS2USI-128-2-0)
{
ICLASS:      VCVTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM:       VCVTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1-mode64-0)
{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1-not64-0)
{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2-0)
{
ICLASS:      VCVTTSD2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1-mode64-0)
{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1-not64-0)
{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2-0)
{
ICLASS:      VCVTTSD2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-mode64-0)
{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-not64-0)
{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-2-0)
{
ICLASS:      VCVTTSH2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-mode64-0)
{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-not64-0)
{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-2-0)
{
ICLASS:      VCVTTSH2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VCVTTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1-mode64-0)
{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1-not64-0)
{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2-0)
{
ICLASS:      VCVTTSS2SI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1-mode64-0)
{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1-not64-0)
{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2-0)
{
ICLASS:      VCVTTSS2USI
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1-mode64-0)
{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR 
PATTERN:     EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1-not64-0)
{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES:  SIMD_SCALAR 
PATTERN:     EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2-0)
{
ICLASS:      VCVTUSI2SD
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-mode64-0)
{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-not64-0)
{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-2-0)
{
ICLASS:      VCVTUSI2SH
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1-mode64-0)
{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1-not64-0)
{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_SCALAR_RC
}


# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2-0)
{
ICLASS:      VCVTUSI2SS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND() mode64 ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
IFORM:       VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_SCALAR_RC
}


# EMITTING VDIVSD (VDIVSD-128-1-0)
{
ICLASS:      VDIVSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VDIVSH (VDIVSH-128-1-0)
{
ICLASS:      VDIVSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VDIVSS (VDIVSS-128-1-0)
{
ICLASS:      VDIVSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFCMADDCSH (VFCMADDCSH-128-1-0)
{
ICLASS:      VFCMADDCSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:     EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC
}


# EMITTING VFCMULCSH (VFCMULCSH-128-1-0)
{
ICLASS:      VFCMULCSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:     EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC
}


# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1-0)
{
ICLASS:      VFIXUPIMMSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC
}


# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1-0)
{
ICLASS:      VFIXUPIMMSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC
}


# EMITTING VFMADD132SD (VFMADD132SD-128-1-0)
{
ICLASS:      VFMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFMADD132SH (VFMADD132SH-128-1-0)
{
ICLASS:      VFMADD132SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFMADD132SS (VFMADD132SS-128-1-0)
{
ICLASS:      VFMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFMADD213SD (VFMADD213SD-128-1-0)
{
ICLASS:      VFMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFMADD213SH (VFMADD213SH-128-1-0)
{
ICLASS:      VFMADD213SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFMADD213SS (VFMADD213SS-128-1-0)
{
ICLASS:      VFMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFMADD231SD (VFMADD231SD-128-1-0)
{
ICLASS:      VFMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFMADD231SH (VFMADD231SH-128-1-0)
{
ICLASS:      VFMADD231SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFMADD231SS (VFMADD231SS-128-1-0)
{
ICLASS:      VFMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFMADDCSH (VFMADDCSH-128-1-0)
{
ICLASS:      VFMADDCSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:     EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC
}


# EMITTING VFMSUB132SD (VFMSUB132SD-128-1-0)
{
ICLASS:      VFMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFMSUB132SH (VFMSUB132SH-128-1-0)
{
ICLASS:      VFMSUB132SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFMSUB132SS (VFMSUB132SS-128-1-0)
{
ICLASS:      VFMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFMSUB213SD (VFMSUB213SD-128-1-0)
{
ICLASS:      VFMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFMSUB213SH (VFMSUB213SH-128-1-0)
{
ICLASS:      VFMSUB213SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFMSUB213SS (VFMSUB213SS-128-1-0)
{
ICLASS:      VFMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFMSUB231SD (VFMSUB231SD-128-1-0)
{
ICLASS:      VFMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFMSUB231SH (VFMSUB231SH-128-1-0)
{
ICLASS:      VFMSUB231SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFMSUB231SS (VFMSUB231SS-128-1-0)
{
ICLASS:      VFMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFMULCSH (VFMULCSH-128-1-0)
{
ICLASS:      VFMULCSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E10
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR 
PATTERN:     EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
IFORM:       VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC
}


# EMITTING VFNMADD132SD (VFNMADD132SD-128-1-0)
{
ICLASS:      VFNMADD132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFNMADD132SH (VFNMADD132SH-128-1-0)
{
ICLASS:      VFNMADD132SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFNMADD132SS (VFNMADD132SS-128-1-0)
{
ICLASS:      VFNMADD132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFNMADD213SD (VFNMADD213SD-128-1-0)
{
ICLASS:      VFNMADD213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFNMADD213SH (VFNMADD213SH-128-1-0)
{
ICLASS:      VFNMADD213SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFNMADD213SS (VFNMADD213SS-128-1-0)
{
ICLASS:      VFNMADD213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFNMADD231SD (VFNMADD231SD-128-1-0)
{
ICLASS:      VFNMADD231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFNMADD231SH (VFNMADD231SH-128-1-0)
{
ICLASS:      VFNMADD231SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFNMADD231SS (VFNMADD231SS-128-1-0)
{
ICLASS:      VFNMADD231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1-0)
{
ICLASS:      VFNMSUB132SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB132SH (VFNMSUB132SH-128-1-0)
{
ICLASS:      VFNMSUB132SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1-0)
{
ICLASS:      VFNMSUB132SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1-0)
{
ICLASS:      VFNMSUB213SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB213SH (VFNMSUB213SH-128-1-0)
{
ICLASS:      VFNMSUB213SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1-0)
{
ICLASS:      VFNMSUB213SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1-0)
{
ICLASS:      VFNMSUB231SD
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB231SH (VFNMSUB231SH-128-1-0)
{
ICLASS:      VFNMSUB231SH
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1-0)
{
ICLASS:      VFNMSUB231SS
CPL:         3
CATEGORY:    VFMA
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VGETEXPSD (VGETEXPSD-128-1-0)
{
ICLASS:      VGETEXPSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VGETEXPSH (VGETEXPSH-128-1-0)
{
ICLASS:      VGETEXPSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VGETEXPSS (VGETEXPSS-128-1-0)
{
ICLASS:      VGETEXPSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VGETMANTSD (VGETMANTSD-128-1-0)
{
ICLASS:      VGETMANTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC
}


# EMITTING VGETMANTSH (VGETMANTSH-128-1-0)
{
ICLASS:      VGETMANTSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC
}


# EMITTING VGETMANTSS (VGETMANTSS-128-1-0)
{
ICLASS:      VGETMANTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC
}


# EMITTING VMAXSD (VMAXSD-128-1-0)
{
ICLASS:      VMAXSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VMAXSH (VMAXSH-128-1-0)
{
ICLASS:      VMAXSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VMAXSS (VMAXSS-128-1-0)
{
ICLASS:      VMAXSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VMINSD (VMINSD-128-1-0)
{
ICLASS:      VMINSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VMINSH (VMINSH-128-1-0)
{
ICLASS:      VMINSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VMINSS (VMINSS-128-1-0)
{
ICLASS:      VMINSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VMULSD (VMULSD-128-1-0)
{
ICLASS:      VMULSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VMULSH (VMULSH-128-1-0)
{
ICLASS:      VMULSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VMULSS (VMULSS-128-1-0)
{
ICLASS:      VMULSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VRANGESD (VRANGESD-128-1-0)
{
ICLASS:      VRANGESD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC
}


# EMITTING VRANGESS (VRANGESS-128-1-0)
{
ICLASS:      VRANGESS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC
}


# EMITTING VREDUCESD (VREDUCESD-128-1-0)
{
ICLASS:      VREDUCESD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC
}


# EMITTING VREDUCESH (VREDUCESH-128-1-0)
{
ICLASS:      VREDUCESH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC
}


# EMITTING VREDUCESS (VREDUCESS-128-1-0)
{
ICLASS:      VREDUCESS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC
}


# EMITTING VRNDSCALESD (VRNDSCALESD-128-1-0)
{
ICLASS:      VRNDSCALESD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
IFORM:       VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC
}


# EMITTING VRNDSCALESH (VRNDSCALESH-128-1-0)
{
ICLASS:      VRNDSCALESH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
IFORM:       VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC
}


# EMITTING VRNDSCALESS (VRNDSCALESS-128-1-0)
{
ICLASS:      VRNDSCALESS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() UIMM8()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
IFORM:       VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC
}


# EMITTING VSCALEFSD (VSCALEFSD-128-1-0)
{
ICLASS:      VSCALEFSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VSCALEFSH (VSCALEFSH-128-1-0)
{
ICLASS:      VSCALEFSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VSCALEFSS (VSCALEFSS-128-1-0)
{
ICLASS:      VSCALEFSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VSQRTSD (VSQRTSD-128-1-0)
{
ICLASS:      VSQRTSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VSQRTSH (VSQRTSH-128-1-0)
{
ICLASS:      VSQRTSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VSQRTSS (VSQRTSS-128-1-0)
{
ICLASS:      VSQRTSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VSUBSD (VSUBSD-128-1-0)
{
ICLASS:      VSUBSD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
IFORM:       VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VSUBSH (VSUBSH-128-1-0)
{
ICLASS:      VSUBSH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
IFORM:       VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VSUBSS (VSUBSS-128-1-0)
{
ICLASS:      VSUBSS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ USES_FTZ 
PATTERN:     EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS:    REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
IFORM:       VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC
}


# EMITTING VUCOMISD (VUCOMISD-128-1-0)
{
ICLASS:      VUCOMISD
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VUCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC
}


# EMITTING VUCOMISH (VUCOMISH-128-1-0)
{
ICLASS:      VUCOMISH
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16
IFORM:       VUCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC
}


# EMITTING VUCOMISS (VUCOMISS-128-1-0)
{
ICLASS:      VUCOMISS
CPL:         3
CATEGORY:    AVX512
EXTENSION:   AVX512EVEX
ISA_SET:     AVX10_2_RC_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
FLAGS:       MUST [  zf-mod pf-mod cf-mod of-0 sf-0 af-0  ]
ATTRIBUTES:  MXCSR SIMD_SCALAR 
PATTERN:     EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VUCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC
}


