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EVEX_INSTRUCTIONS()::
# EMITTING VCVTTPD2DQS (VCVTTPD2DQS-128-1)
{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
IFORM:       VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512
}

{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL128 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128
}


# EMITTING VCVTTPD2DQS (VCVTTPD2DQS-256-1)
{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL256 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL256 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256
}


# EMITTING VCVTTPD2DQS (VCVTTPD2DQS-512-1)
{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL512 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL512 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTTPD2QQS (VCVTTPD2QQS-128-1)
{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
IFORM:       VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512
}

{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL128 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512
}


# EMITTING VCVTTPD2QQS (VCVTTPD2QQS-256-1)
{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL256 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512
}


# EMITTING VCVTTPD2QQS (VCVTTPD2QQS-512-1)
{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL512 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512
}


# EMITTING VCVTTPD2UDQS (VCVTTPD2UDQS-128-1)
{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
IFORM:       VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL128 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128
}


# EMITTING VCVTTPD2UDQS (VCVTTPD2UDQS-256-1)
{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL256 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL256 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256
}


# EMITTING VCVTTPD2UDQS (VCVTTPD2UDQS-512-1)
{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL512 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL512 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512
}


# EMITTING VCVTTPD2UQQS (VCVTTPD2UQQS-128-1)
{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
IFORM:       VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL128 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512
}


# EMITTING VCVTTPD2UQQS (VCVTTPD2UQQS-256-1)
{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
IFORM:       VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL256 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512
}


# EMITTING VCVTTPD2UQQS (VCVTTPD2UQQS-512-1)
{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
IFORM:       VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512
}

{
ICLASS:      VCVTTPD2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W1 VL512 NOEVSR ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
IFORM:       VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512
}


# EMITTING VCVTTPS2DQS (VCVTTPS2DQS-128-1)
{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2DQS (VCVTTPS2DQS-256-1)
{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2DQS (VCVTTPS2DQS-512-1)
{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2DQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2QQS (VCVTTPS2QQS-128-1)
{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2QQS (VCVTTPS2QQS-256-1)
{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:i64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2QQS (VCVTTPS2QQS-512-1)
{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2QQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2UDQS (VCVTTPS2UDQS-128-1)
{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2UDQS (VCVTTPS2UDQS-256-1)
{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2UDQS (VCVTTPS2UDQS-512-1)
{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
IFORM:       VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UDQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2UQQS (VCVTTPS2UQQS-128-1)
{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL128 NOEVSR
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_128
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL128 NOEVSR ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2UQQS (VCVTTPS2UQQS-256-1)
{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL256 NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=0 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN256() SAE256() NOEVSR
OPERANDS:    REG0=YMM_R3():w:qq:u64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
IFORM:       VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_256
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL256 NOEVSR ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTPS2UQQS (VCVTTPS2UQQS-512-1)
{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN512() SAE() NOEVSR
OPERANDS:    REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
IFORM:       VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512
}

{
ICLASS:      VCVTTPS2UQQS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_512
EXCEPTIONS:  AVX512-E2
REAL_OPCODE: Y
ATTRIBUTES:  BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ 
PATTERN:     EVV 0x6C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UBIT=1 W0 VL512 NOEVSR ESIZE_32_BITS() NELEM_HALF()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
IFORM:       VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512
}


# EMITTING VCVTTSD2SIS (VCVTTSD2SIS-128-1-mode64)
{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SIS_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SIS_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_Q MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
IFORM:       VCVTTSD2SIS_GPR32i32_MEMf64_AVX512
}


# EMITTING VCVTTSD2SIS (VCVTTSD2SIS-128-1-not64)
{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SIS_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SIS_GPR32i32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_Q MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
IFORM:       VCVTTSD2SIS_GPR32i32_MEMf64_AVX512
}


# EMITTING VCVTTSD2SIS (VCVTTSD2SIS-128-2)
{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SIS_GPR64i64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2SIS_GPR64i64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_Q MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
IFORM:       VCVTTSD2SIS_GPR64i64_MEMf64_AVX512
}


# EMITTING VCVTTSD2USIS (VCVTTSD2USIS-128-1-mode64)
{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USIS_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USIS_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_Q MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
IFORM:       VCVTTSD2USIS_GPR32u32_MEMf64_AVX512
}


# EMITTING VCVTTSD2USIS (VCVTTSD2USIS-128-1-not64)
{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USIS_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USIS_GPR32u32_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_Q MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
IFORM:       VCVTTSD2USIS_GPR32u32_MEMf64_AVX512
}


# EMITTING VCVTTSD2USIS (VCVTTSD2USIS-128-2)
{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USIS_GPR64u64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM:       VCVTTSD2USIS_GPR64u64_XMMf64_AVX512
}

{
ICLASS:      VCVTTSD2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_Q MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
IFORM:       VCVTTSD2USIS_GPR64u64_MEMf64_AVX512
}


# EMITTING VCVTTSS2SIS (VCVTTSS2SIS-128-1-mode64)
{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SIS_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SIS_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
IFORM:       VCVTTSS2SIS_GPR32i32_MEMf32_AVX512
}


# EMITTING VCVTTSS2SIS (VCVTTSS2SIS-128-1-not64)
{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SIS_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SIS_GPR32i32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_ONE()
OPERANDS:    REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
IFORM:       VCVTTSS2SIS_GPR32i32_MEMf32_AVX512
}


# EMITTING VCVTTSS2SIS (VCVTTSS2SIS-128-2)
{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SIS_GPR64i64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2SIS_GPR64i64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2SIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
IFORM:       VCVTTSS2SIS_GPR64i64_MEMf32_AVX512
}


# EMITTING VCVTTSS2USIS (VCVTTSS2USIS-128-1-mode64)
{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USIS_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USIS_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W0 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
IFORM:       VCVTTSS2USIS_GPR32u32_MEMf32_AVX512
}


# EMITTING VCVTTSS2USIS (VCVTTSS2USIS-128-1-not64)
{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USIS_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
OPERANDS:    REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USIS_GPR32u32_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_ONE()
OPERANDS:    REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
IFORM:       VCVTTSS2USIS_GPR32u32_MEMf32_AVX512
}


# EMITTING VCVTTSS2USIS (VCVTTSS2USIS-128-2)
{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USIS_GPR64u64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 FIX_ROUND_LEN128() SAE() mode64 NOEVSR ZEROING=0 MASK=0 EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM:       VCVTTSS2USIS_GPR64u64_XMMf32_AVX512
}

{
ICLASS:      VCVTTSS2USIS
CPL:         3
CATEGORY:    CONVERT
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_SAT_CVT_DS_SCALAR
EXCEPTIONS:  AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES:  DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR USES_DAZ 
PATTERN:     EVV 0x6C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 FIX_ROUND_LEN128() mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_ONE() EVEXR4_ONE()
OPERANDS:    REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
IFORM:       VCVTTSS2USIS_GPR64u64_MEMf32_AVX512
}


