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EVEX_INSTRUCTIONS()::
# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-1)
{
ICLASS:      VPCOMPRESSB
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_ONE()
OPERANDS:    MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8
IFORM:       VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512
}


# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-2)
{
ICLASS:      VPCOMPRESSB
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8
IFORM:       VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512
}


# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-1)
{
ICLASS:      VPCOMPRESSB
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_ONE()
OPERANDS:    MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8
IFORM:       VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512
}


# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-2)
{
ICLASS:      VPCOMPRESSB
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8
IFORM:       VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512
}


# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-1)
{
ICLASS:      VPCOMPRESSB
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ZEROING=0  ESIZE_8_BITS() NELEM_ONE()
OPERANDS:    MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8
IFORM:       VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512
}


# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-2)
{
ICLASS:      VPCOMPRESSB
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8
IFORM:       VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512
}


# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-1)
{
ICLASS:      VPCOMPRESSW
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
IFORM:       VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512
}


# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-2)
{
ICLASS:      VPCOMPRESSW
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1  NOEVSR 
OPERANDS:    REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
IFORM:       VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512
}


# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-1)
{
ICLASS:      VPCOMPRESSW
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
IFORM:       VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512
}


# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-2)
{
ICLASS:      VPCOMPRESSW
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1  NOEVSR 
OPERANDS:    REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
IFORM:       VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512
}


# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-1)
{
ICLASS:      VPCOMPRESSW
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ZEROING=0  ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
IFORM:       VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512
}


# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-2)
{
ICLASS:      VPCOMPRESSW
CPL:         3
CATEGORY:    COMPRESS
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
IFORM:       VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512
}


# EMITTING VPEXPANDB (VPEXPANDB-128-1)
{
ICLASS:      VPEXPANDB
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W0  NOEVSR  ESIZE_8_BITS() NELEM_ONE()
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
IFORM:       VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VPEXPANDB (VPEXPANDB-128-2)
{
ICLASS:      VPEXPANDB
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
IFORM:       VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512
}


# EMITTING VPEXPANDB (VPEXPANDB-256-1)
{
ICLASS:      VPEXPANDB
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W0  NOEVSR  ESIZE_8_BITS() NELEM_ONE()
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
IFORM:       VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VPEXPANDB (VPEXPANDB-256-2)
{
ICLASS:      VPEXPANDB
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
IFORM:       VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512
}


# EMITTING VPEXPANDB (VPEXPANDB-512-1)
{
ICLASS:      VPEXPANDB
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W0  NOEVSR  ESIZE_8_BITS() NELEM_ONE()
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
IFORM:       VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512
}


# EMITTING VPEXPANDB (VPEXPANDB-512-2)
{
ICLASS:      VPEXPANDB
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
IFORM:       VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512
}


# EMITTING VPEXPANDW (VPEXPANDW-128-1)
{
ICLASS:      VPEXPANDW
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1  NOEVSR  ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
IFORM:       VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VPEXPANDW (VPEXPANDW-128-2)
{
ICLASS:      VPEXPANDW
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1  NOEVSR 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
IFORM:       VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512
}


# EMITTING VPEXPANDW (VPEXPANDW-256-1)
{
ICLASS:      VPEXPANDW
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1  NOEVSR  ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
IFORM:       VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VPEXPANDW (VPEXPANDW-256-2)
{
ICLASS:      VPEXPANDW
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1  NOEVSR 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
IFORM:       VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512
}


# EMITTING VPEXPANDW (VPEXPANDW-512-1)
{
ICLASS:      VPEXPANDW
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP 
PATTERN:    EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1  NOEVSR  ESIZE_16_BITS() NELEM_ONE()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
IFORM:       VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512
}


# EMITTING VPEXPANDW (VPEXPANDW-512-2)
{
ICLASS:      VPEXPANDW
CPL:         3
CATEGORY:    EXPAND
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1  NOEVSR 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
IFORM:       VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512
}


# EMITTING VPSHLDD (VPSHLDD-128-1)
{
ICLASS:      VPSHLDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
IFORM:       VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
}

{
ICLASS:      VPSHLDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPSHLDD (VPSHLDD-256-1)
{
ICLASS:      VPSHLDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
IFORM:       VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
}

{
ICLASS:      VPSHLDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPSHLDD (VPSHLDD-512-1)
{
ICLASS:      VPSHLDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPSHLDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPSHLDQ (VPSHLDQ-128-1)
{
ICLASS:      VPSHLDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
IFORM:       VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
}

{
ICLASS:      VPSHLDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPSHLDQ (VPSHLDQ-256-1)
{
ICLASS:      VPSHLDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
IFORM:       VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
}

{
ICLASS:      VPSHLDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPSHLDQ (VPSHLDQ-512-1)
{
ICLASS:      VPSHLDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPSHLDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPSHLDVD (VPSHLDVD-128-1)
{
ICLASS:      VPSHLDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
IFORM:       VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
}

{
ICLASS:      VPSHLDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
}


# EMITTING VPSHLDVD (VPSHLDVD-256-1)
{
ICLASS:      VPSHLDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
IFORM:       VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
}

{
ICLASS:      VPSHLDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
}


# EMITTING VPSHLDVD (VPSHLDVD-512-1)
{
ICLASS:      VPSHLDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPSHLDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSHLDVQ (VPSHLDVQ-128-1)
{
ICLASS:      VPSHLDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
IFORM:       VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}

{
ICLASS:      VPSHLDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}


# EMITTING VPSHLDVQ (VPSHLDVQ-256-1)
{
ICLASS:      VPSHLDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
IFORM:       VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}

{
ICLASS:      VPSHLDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}


# EMITTING VPSHLDVQ (VPSHLDVQ-512-1)
{
ICLASS:      VPSHLDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPSHLDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSHLDVW (VPSHLDVW-128-1)
{
ICLASS:      VPSHLDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
IFORM:       VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
}

{
ICLASS:      VPSHLDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1    ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
IFORM:       VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
}


# EMITTING VPSHLDVW (VPSHLDVW-256-1)
{
ICLASS:      VPSHLDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   
OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
IFORM:       VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
}

{
ICLASS:      VPSHLDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1    ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
IFORM:       VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
}


# EMITTING VPSHLDVW (VPSHLDVW-512-1)
{
ICLASS:      VPSHLDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
IFORM:       VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
}

{
ICLASS:      VPSHLDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
IFORM:       VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
}


# EMITTING VPSHLDW (VPSHLDW-128-1)
{
ICLASS:      VPSHLDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
IFORM:       VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
}

{
ICLASS:      VPSHLDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
IFORM:       VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
}


# EMITTING VPSHLDW (VPSHLDW-256-1)
{
ICLASS:      VPSHLDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
IFORM:       VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
}

{
ICLASS:      VPSHLDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
IFORM:       VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
}


# EMITTING VPSHLDW (VPSHLDW-512-1)
{
ICLASS:      VPSHLDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
IFORM:       VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
}

{
ICLASS:      VPSHLDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
IFORM:       VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
}


# EMITTING VPSHRDD (VPSHRDD-128-1)
{
ICLASS:      VPSHRDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
IFORM:       VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
}

{
ICLASS:      VPSHRDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPSHRDD (VPSHRDD-256-1)
{
ICLASS:      VPSHRDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
IFORM:       VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
}

{
ICLASS:      VPSHRDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPSHRDD (VPSHRDD-512-1)
{
ICLASS:      VPSHRDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
IFORM:       VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
}

{
ICLASS:      VPSHRDD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0   UIMM8()  ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
}


# EMITTING VPSHRDQ (VPSHRDQ-128-1)
{
ICLASS:      VPSHRDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
IFORM:       VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
}

{
ICLASS:      VPSHRDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPSHRDQ (VPSHRDQ-256-1)
{
ICLASS:      VPSHRDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
IFORM:       VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
}

{
ICLASS:      VPSHRDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPSHRDQ (VPSHRDQ-512-1)
{
ICLASS:      VPSHRDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
IFORM:       VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
}

{
ICLASS:      VPSHRDQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1   UIMM8()  ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
IFORM:       VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
}


# EMITTING VPSHRDVD (VPSHRDVD-128-1)
{
ICLASS:      VPSHRDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W0   
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
IFORM:       VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
}

{
ICLASS:      VPSHRDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
}


# EMITTING VPSHRDVD (VPSHRDVD-256-1)
{
ICLASS:      VPSHRDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W0   
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
IFORM:       VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
}

{
ICLASS:      VPSHRDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
}


# EMITTING VPSHRDVD (VPSHRDVD-512-1)
{
ICLASS:      VPSHRDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W0   
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
IFORM:       VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}

{
ICLASS:      VPSHRDVD
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W0    ESIZE_32_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
IFORM:       VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}


# EMITTING VPSHRDVQ (VPSHRDVQ-128-1)
{
ICLASS:      VPSHRDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
IFORM:       VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}

{
ICLASS:      VPSHRDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL128  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}


# EMITTING VPSHRDVQ (VPSHRDVQ-256-1)
{
ICLASS:      VPSHRDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
IFORM:       VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}

{
ICLASS:      VPSHRDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL256  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}


# EMITTING VPSHRDVQ (VPSHRDVQ-512-1)
{
ICLASS:      VPSHRDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM:       VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}

{
ICLASS:      VPSHRDVQ
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED 
PATTERN:    EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn]  MODRM()  VL512  W1    ESIZE_64_BITS() NELEM_FULL()
OPERANDS:    REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM:       VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}


# EMITTING VPSHRDVW (VPSHRDVW-128-1)
{
ICLASS:      VPSHRDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   
OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
IFORM:       VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
}

{
ICLASS:      VPSHRDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1    ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
IFORM:       VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
}


# EMITTING VPSHRDVW (VPSHRDVW-256-1)
{
ICLASS:      VPSHRDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   
OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
IFORM:       VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
}

{
ICLASS:      VPSHRDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1    ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
IFORM:       VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
}


# EMITTING VPSHRDVW (VPSHRDVW-512-1)
{
ICLASS:      VPSHRDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   
OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
IFORM:       VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
}

{
ICLASS:      VPSHRDVW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1    ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
IFORM:       VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
}


# EMITTING VPSHRDW (VPSHRDW-128-1)
{
ICLASS:      VPSHRDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL128  W1   UIMM8() 
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
IFORM:       VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
}

{
ICLASS:      VPSHRDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_128
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL128  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
IFORM:       VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
}


# EMITTING VPSHRDW (VPSHRDW-256-1)
{
ICLASS:      VPSHRDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL256  W1   UIMM8() 
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
IFORM:       VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
}

{
ICLASS:      VPSHRDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_256
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL256  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
IFORM:       VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
}


# EMITTING VPSHRDW (VPSHRDW-512-1)
{
ICLASS:      VPSHRDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MASKOP_EVEX 
PATTERN:    EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn]  VL512  W1   UIMM8() 
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
IFORM:       VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
}

{
ICLASS:      VPSHRDW
CPL:         3
CATEGORY:    VBMI2
EXTENSION:   AVX512EVEX
ISA_SET:     AVX512_VBMI2_512
EXCEPTIONS:     AVX512-E4
REAL_OPCODE: Y
ATTRIBUTES:  MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM 
PATTERN:    EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] BCRC=0 MODRM()  VL512  W1   UIMM8()  ESIZE_16_BITS() NELEM_FULLMEM()
OPERANDS:    REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
IFORM:       VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
}


